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1 ASIC 验证技术 ................................................. 1 1.1 ASIC 设计流程 ............................................... 1 1.2 FPGA 验证技术 ............................................... 3 1.3 Altera 与 Xilinx 工具对比 ................................... 3 1.4 VHDL 与 Verilog 对比 ....................................... 5 1.5 Verilog 良好编程习惯 ........................................ 6 2 基于 ALTERA 的 ASIC 验证 ................................. 9 2.1 Stratix IV FPGA 资源与架构 ................................ 9 2.2 QuartusII 设计工具 ......................................... 10 2.3 ASIC 设计转换 .............................................. 11 2.3.1 PLL 设计 ...................................................... 11 2.3.1 RAM 设计 ..................................................... 16 2.4 时序约束 ................................................... 19 2.4.1 QSF&Tcl ....................................................... 22 2.4.2 LogicLock ........................................................ 23 2.5 综合布局布线 ............................................... 23 2.5.1 综合设置 ........................................................ 24 2.5.2 增量编译 ......................................................... 25 2.5.3 VQM & QXP ..................................................... 30 2.5.4 时序分析 ............................................................ 30 2.6 下载设计文件 ............................................... 32 2.7 Debug ...................................................... 32 2.7.1 In-System Memory Content Editor ..................... 33 2.7.2 ChipPlanner ............................................................... 34 2.7.3 SignalTapII ................................................................. 38 2.7.4 Keep Signals .............................................................. 43 2.8 Example 工程 ............................................... 45 3 基于 XILINX 的 ASIC 验证 ................................................... 49 3.1 Vertex-7 FPGA 资源与架构 ................................... 49 3.2 设计工具 ISE 与 Vivado ...................................... 49 3.3 ASIC 设计转换 .............................................. 54 3.3.1 时钟资源 ........................................................ 54 3.3.2 PLL 设计 ........................................................... 58 3.3.3 RAM 设计 .................................................61 3.4 时序约束 ................................................... 64 3.5 综合布局布线 ............................................... 70 3.5.1 Blackbox ............................................................ 70 3.5.2 Keep Signals ..................................................... 71 3.5.3 Strategies .......................................................... 72 3.5.4 Incremental Compile ....................................... 75 3.5.5 时序分析 .................................................... 77 3.5.6 Generate Bitstream ...................................81 3.6 下载设计文件 ............................................... 84 3.6.1 下载 bit 文件 ............................................ 84 3.6.2 下载 mcs 文件 ......................................... 87 3.7 Debug ...................................................... 88 3.8 Example 工程 ............................................... 94 3.8.1 导入 ISE & Synplify 工程 ................................... 94 3.8.2 Working with Tcl ........................................... 95 3.9 Gate Clock 处理 ............................................ 99 3.10 多片 FPGA 验证 ............................................ 101 4 DDR 相关技术 ................................................ 104 4.1 DDR Controller ............................................ 108 4.2 DDR PHY ................................................... 111 4.2.1 Altera PHY .............................................. 111 4.2.2 Xilinx PHY ............................................... 113 5 硬件技术 ...................................................... 117 5.1 PCB 设计注意事项 .......................................... 117 5.2 电磁兼容与信号完整性 ...................................... 117 5.2.1 端接匹配 ................................................... 118 5.2.2 防止地弹 ......................................................118 5.2.3 减小串扰 .................................................... 118 5.2.4 降低电磁干扰 .............................................. 119 5.3 FPGA 开发板使用注意事项 .................................. 120 总结 ................................................................... 121
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