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/**************************************************************************//**
* @file main.c * @version V2.10 * $Revision: 2 $ * $Date: 16/10/25 4:29p $ * @brief Hardware divider(HDIV) Sample Code * * @note * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * ******************************************************************************/ #include #include "NUC029xGE.h" #define PLLCON_SETtiNG CLK_PLLCON_72MHz_HXT #define PLL_CLOCK 72000000 void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Select HCLK clock source as HIRC and and HCLK source divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/ CLK_DisablePLL(); /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set multi-function pins for UART0 RXD and TXD */ SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk); SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA3MFP_UART0_RXD | SYS_GPA_MFPL_PA2MFP_UART0_TXD); } void UART0_Init() { /*---------------------------------------------------------------------------------------------------------*/ /* Init UART */ /*---------------------------------------------------------------------------------------------------------*/ UART_Open(UART0, 115200); } void HDIV_Init(void) { /* Enable Hardware Divider Clock */ CLK->AHBCLK |= CLK_AHBCLK_HDIVCKEN_Msk; } /*---------------------------------------------------------------------------------------------------------*/ /* MAIN function */ /*---------------------------------------------------------------------------------------------------------*/ int main(void) { /* Disable register write-protection function */ SYS_UnlockReg(); /* Init System, IP clock and multi-function I/O */ SYS_Init(); /* Init UART0 for printf */ UART0_Init(); /* Init Divider */ HDIV_Init(); printf("+----------------------------------------------+\n"); printf("| Hardware Divider(HDIV) Sample Code |\n"); printf("+----------------------------------------------+\n"); printf("\n"); printf("12341 / 123 = %d\n", HDIV_Div(12341, 123)); printf("12341 %% 123 = %d\n", HDIV_Mod(12341, 123)); /* Lock protected registers */ SYS_LockReg(); printf("Done\n"); while(SYS->PDID); return 0; } /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ |
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