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hi JSW,
请检查下晶体选型和电路设计。 1)参考TVP5160的器件手册P98,晶体的指标是:标称频率14.31818MHz,频偏允许范围+/-50PPM。可以尝试换颗晶体试下? 2)电路设计参考器件手册P22,注意正确选择外部的电容和电阻参数。电容关系是CL1 = CL2 = 2CL – CSTRAY,电阻推荐是100Kohms。 谢谢。 best regards, Steven 3.16 Clock Circuits An internal line-locked PLL generates the system clock (SCLK). A 14.31818-MHz clock is required to drive the PLL. This may be input to the TVP5160AM1 decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 3-8 shows the reference clock configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental frequency), the external capacitors must have the following relationship: CL1 = CL2 = 2CL – CSTRAY where CSTRAY is the terminal capacitance with respect to ground, and CL is the crystal load capacitance specified by the crystal manufacturer. Figure 3-8 shows the reference clock configurations. NOTE: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-kΩ resistor may be used for most crystal types. Clock source frequency should have an accuracy of ±50 ppm (max). |
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